The present invention relates to the deposition of halogen-doped dielectric layers during wafer processing and more specifically to a method and apparatus for forming a halogen-doped layer having a low dielectric constant and high film stability.
One of the primary steps in the fabrication of modern semiconductor devices is the formation of a thin film on a semiconductor substrate by chemical reaction of gases. Such a deposition process is referred to as chemical vapor deposition or "CVD". Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions produce a desired film. The high temperatures at which thermal CVD processes operate can damage device structures having metal layers. A common plasma enhanced CVD (PECVD) processes, on the other hand, promote disassociation of the reactant gases by the application of radio frequency (RF) energy to a reaction zone proximate to the substrate surface, thereby creating a plasma of highly reactive ionic species. The high reactivity of the released ionic species reduces the energy required for a chemical reaction to take place, and thus lowers the required temperature for such CVD processes. The relatively low temperature of a PECVD process makes such processes ideal for the formation of insulating layers over deposited metal layers and for the formation of other insulating layers.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called "Moore's Law") which means that the number of devices which will fit on a chip doubles every two years. Today's wafer fabrication plants are routinely producing integrated circuits having 0.5 and even 0.35 micron feature sizes, and tomorrow's plants soon will be producing devices having even smaller geometries.
As device sizes become smaller and integration density increases, issues which were not previously considered important by the industry are becoming of concern. With the advent of multilevel metal technology in which three, four, or more layers of metal are formed on the semiconductors, one goal of semiconductor manufacturers is lowering the dielectric constant of insulating layers such as intermetal dielectric layers. Low dielectric constant films are particularly desirable for intermetal dielectric (IMD) layers to reduce the RC time delay of the interconnect metallization, to prevent cross-talk between the different levels of metallization, and to reduce device power consumption.
Many approaches to obtain lower dielectric constants have been proposed. One of the more promising solutions is the incorporation of fluorine or other halogen elements, such as chlorine or bromine, into a silicon oxide layer. In addition to the related application set forth above, another example of halogen incorporation is described in U.S. Ser. No. 08/548,391 now abandoned entitled "METHOD AND APPARATUS FOR IMPROVING FILM STABILITY OF HALOGEN-DOPED SILICON OXIDE FILMS" and assigned to Applied Materials, Inc. The Ser. No. 08/548,391 application was filed on Oct. 25, 1995, and is hereby incorporated by reference for all purposes.
It is believed that fluorine, the preferred halogen dopant for silicon oxide films, lowers the dielectric constant of the silicon oxide film because fluorine is an electronegative atom that decreases the polarizability of the overall SiOF network. Fluorine-doped silicon oxide films are also referred to as fluoro silicate glass (FSG) films. The Ser. No. 08/548,391 and 08/538,696 patent applications disclose FSG films deposited from a process gas that includes TEOS (Si(OC.sub.2 H.sub.5).sub.4) mixed with a helium carrier gas, oxygen (O.sub.2) and a fluorine source. Each application discloses introducing the helium carrier gas at a rate of between 400-1500 sccm, but neither application or other known prior art recognizes any notable benefits to introducing helium at a particular rate.
In addition to decreasing the dielectric constant, incorporating fluorine in intermetal silicon oxide layers also helps solve common problems encountered in fabricating smaller geometry devices, such as filling closely spaced gaps on semiconductor structures. Because fluorine is an etching species, it is believed that fluorine doping introduces an etching effect on the growing film. This simultaneous deposition/etching effect allows FSG films to have improved gap filling capabilities such that the films are able to adequately cover adjacent metal layers having an aspect ratio of 1.8 or more.
Thus, manufacturers desire to include fluorine in various dielectric layers and particularly in intermetal dielectric layers. One problem encountered in the deposition of FSG layers is film stability. Loosely bound fluorine atoms in the lattice structure of some FSG films result in the films' having a tendency to absorb moisture. The absorbed moisture increases the film's dielectric constant and can cause further problems when the film is exposed to a thermal process such as an anneal process. The high temperature of the thermal processes can move the absorbed water molecules and loosely bound fluorine atoms out of the oxide layer through metal or other subsequently deposited layers. The excursion of molecules and atoms in this manner is referred to as outgassing.
From the above, it can be seen that an oxide film having a low dielectric constant is necessary to keep pace with emerging technologies. It can also be seen that a method of increasing the stability of halogen-doped oxide films, thereby reducing moisture absorption and outgassing in the films, is desirable.